One technique of examining and verifying a design of a hardware component such as an integrated circuit is to model operation of the design in software. For the purpose of modeling the design, its functionality may be described as procedures, for example, using a hardware design language (HDL). For example, HDL may represent various functions or operations of the hardware design as separate models or statements in the HDL code.
The software emulation of the hardware (referred to, hereinafter as “source code”) may be operated in different configurations to test or verify operation of various functionalities of the component. A test may cause execution of all or some of the statements of the HDL code. A fraction or percentage of the statements or other entities in the HDL code that are covered by a test may be referred to as coverage. Coverage may relate to the entire set of HDL code, or to a part or block of HDL code. Coverage may refer to code (e.g., whether a block of code has been executed during a test), expressions (e.g., whether all possibilities in a truth table have been covered by a test), functionality, or other facets of the emulation.
Metric-driven verification (MDV) is concerned with analyzing what needs to be verified in a device under test (DUT) and how, and setting metrics that would allow determining the progress towards converging to desired goals. Such goals may be, for example, desired coverage level or levels.
A user may wish to exclude one or a plurality of entities from a calculation of the metric driven verification score, for various reasons.